`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:54:02 03/31/2014 
// Design Name: 
// Module Name:    ClockDivider 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module ClockDivider(clk, level_clk, difficulty);

input clk;
input [3:0] difficulty;

output reg level_clk;

reg [20:0] count;   //initial frequency is 100MHz, changing it from 100MHz to 50MHz, 25MHz...
always @ (posedge clk) begin
      count <= count + 1'b1;
	
		case(difficulty) //a smaller count meaning less dividing with higher frequency is a high difficulty
			0: level_clk = count[19];
			1: level_clk = count[18];
			2: level_clk = count[17];
			3: level_clk = count[16];
			4: level_clk = count[5];
			5: level_clk = count[3];
		endcase
	end
	



endmodule
